1. Field of the Invention
The present invention relates to a semiconductor device including a CMOS transistor, a resistor, and a fuse for laser trimming.
2. Description of the Related Art
In a highly accurate analog IC used for a voltage detector or the like, a transistor and a resistor are combined in order to obtain desired characteristics. To accomplish this, a measure generally taken involves blowing out a fuse for laser trimming formed of, for example, a polycrystalline silicon thin film by laser radiation. By this measure, the combination pattern of resistors is adjusted in order to adjust variations in characteristics during a pre-process stage of the manufacture of the analog IC, such as during processing of a semiconductor wafer or adjustment of a target value.
Such a fuse for laser trimming in an analog IC is described with reference to FIG. 4 to FIG. 6. FIG. 4 is a plan view, FIG. 5 is a schematic sectional view taken along the line C-C, and FIG. 6 is a schematic sectional view taken along the line D-D. A fuse 206 formed of a polycrystalline silicon thin-film resistor is provided on a field insulating film 203 formed on a surface of a P-type semiconductor substrate 201. A nitride film 220 and an oxide film 219 as protective films and interlayer insulating films 216 and 214 among multilayer wirings are partly etched from the surface thereof to form a fuse opening 222 so that a laser can be radiated to the fuse 206. In the fuse opening 222, side walls of the nitride film, the interlayer insulating films, and the like are exposed. In a multilayer wiring process which is a double or more metal process, as a technology for planarization, for example, a technology is used in which, after coating an SOG layer formed of spin-on-glass (SOG), etching back is performed. SOG has excellent characteristics as a material used for etching back, but, generally, has the feature of being high in hygroscopicity. Because of that, when, after the etching back, an SOG layer 217 between the stacked interlayer insulating films remains, moisture enters through the SOG layer, which may cause fluctuations in element characteristics of the IC, resulting in occurrence of a problem related to the long-term reliability. In particular, in a PMOS transistor, it is known that negative bias temperature instability (NBTI) which is caused when a negative gate bias is applied in a high temperature state causes a shift of the threshold voltage of the transistor.
The fuse opening is further described below. By adjusting the thickness of an interlayer insulating film above the fuse by patterning by photolithography and then etching the fuse opening 222, prevention of defective trimming such as insufficient cut in the laser trimming is sought. In a related-art structure, after the passivation nitride film 220 as the final protective film is deposited, the passivation nitride film 220 in the fuse opening 222 and a pad portion (not shown) is partly removed, and then, etching is performed again so that the interlayer insulating film above the fuse has a predetermined thickness.
It is noted that rings 221 formed of first and second metal wirings for preventing entry of moisture are provided between the fuse opening 222 and an IC chip. The guard rings 221 are provided, and the SOG layer 217 used as an interlayer insulating film is cut so as to be prevented from reaching the inside of the chip as illustrated in FIG. 5.
However, an oxide film as an insulating film is exposed at the side walls of the interlayer insulating films in the fuse opening. In the insulating film layer in which etching back of the SOG is performed, the SOG layer is exposed. It follows that entry of moisture occurs, which may result in not only NBTI but also corrosion of metal wiring or the like, leading to deterioration of characteristics of the IC.
For example, Japanese Published Patent Application Hei 05-63091 and Hei 07-22508 disclose measures for preventing entry of moisture by forming a guard ring using a metal as a barrier from the fuse opening to the inside of the IC, in order to prevent deterioration of the long-term reliability owing to such entry of moisture through the fuse opening.
In an analog IC, size reduction of each component is indispensable for reducing the chip size. If the distance from the fuse opening is secured for the purpose of inhibiting fluctuations in element characteristics and corrosion of metal wiring owing to entry of moisture through a fuse portion, the chip size is increased to lose competitiveness.
Further, with regard to a measure of forming a guard ring as a barrier using metal wiring for the purpose of preventing entry of moisture through the SOG, a shift of characteristics caused by NBTI or the like is effectively inhibited, but, because the SOG layer is exposed in the fuse opening, the guard ring of metal wiring may cause corrosion of wiring.